Applied Materials, the largest maker of semiconductor manufacturing equipment, has unveiled chip wiring innovations that aim to address challenges in energy-efficient computing. These innovations involve the use of new materials in chip wiring, which will enable two-nanometer node manufacturing. With the width between circuits being around two billionths of a meter apart, these advancements will reduce resistance in wiring by up to 25% and chip capacitance by up to 3%.
## The Need for New Materials in Chip Development
According to Alex Jansen, Director of Product Marketing at Applied Materials, the chip industry has been able to achieve a threefold improvement every two years over the past 15 years. However, to continue this trend, new materials are necessary. Jansen emphasizes that there are several ways to achieve this, including focusing on patterning, transistors, wiring, and advanced packaging. In this case, Applied Materials is specifically focusing on wiring.
## The Importance of Chip Wiring
Modern chips consist of more than 60 miles of copper interconnect and multiple layers of wiring. Chip makers are constantly striving to improve the performance and power efficiency of these chips by enhancing the wiring. Each chip is essentially a vast 3D network of wires, making wiring a critical component in achieving energy-efficient computing.
## Materials Engineering Innovations for Increased Performance
Applied Materials’ materials engineering innovations aim to increase the performance-per-watt of computer systems by enabling copper wiring to scale to the 2nm logic node and beyond. These innovations include the use of an enhanced version of Black Diamond, a low-dielectric-constant film that reduces the buildup of electrical charges and interference between electrical signals. Additionally, Applied Materials has developed a binary metal combination of ruthenium and cobalt (RuCo) for the liner between the copper and the film, reducing liner thickness by up to 33% and improving chip performance and power consumption.
## Overcoming Challenges in Chip Scaling
As chip manufacturing scales to 2nm and below, thinner dielectric materials and narrower copper wires create challenges. Thinner dielectric materials make chips mechanically weaker, while narrower copper wires lead to increased electrical resistance that can reduce chip performance and increase power consumption. Applied Materials’ innovations in low-k dielectric materials and copper wiring aim to overcome these challenges, enabling chip scaling to the most advanced nodes while improving overall system performance and power efficiency.
## The Promise of Better Wiring for AI Chips
The advancements in chip wiring are crucial for the development of better graphics processing units (GPUs) and other artificial intelligence (AI) chips. These chips need to handle the demands of AI computing and high-bandwidth memory. The new chip wiring products, along with other materials engineering innovations, will enable the chip industry to continue achieving three times improvement every two years for energy efficiency.
## Conclusion
Applied Materials’ chip wiring innovations offer significant advancements in the field of energy-efficient computing. By introducing new materials and enhancing existing ones, these innovations enable chip manufacturers to scale to the most advanced nodes while improving performance, power consumption, and overall system efficiency. With the demand for better GPUs and AI chips on the rise, these advancements are crucial for meeting the requirements of future computing technologies.
